1. The Field of the Invention
The present invention relates to methods for forming silicon structures. More particularly, the present invention relates to methods for forming a silicon structure of increased surface area by forming roughen ed surfaces on opposite sides of the silicon structure. The present invention is also directed to a capacitor having capacitor plates that similarly have an increased surface area on opposite sides thereof.
2. The Relevant Technology
Integrated circuits are found on micro chips and provide the logic and memory of computers and other such intelligent electronic devices. These integrated circuits are now being formed with an improved efficiency that has made computers and other intelligent electronic devices more affordable. Continual progress in integrated circuit manufacturing processes has also led to an increasingly smaller scale and a greater functionality of intelligent electronic devices.
Integrated circuits are currently manufactured by an elaborate process in which semiconductor devices, insulating films, and patterned conducting films are sequentially constructed in a predetermined arrangement on a semiconductor substrate. In the context of this document, the term xe2x80x9csemiconductor substratexe2x80x9d is defined to mean any construction comprising semi conductive material, including but not limited to bulk semi conductive material such as a semi conductive wafer, either alone or in assemblies comprising other materials thereon, and semi conductive material layers, either alone or in assemblies comprising other materials. The term xe2x80x9csubstratexe2x80x9d refers to any supporting structure including but not limited to the semiconductor substrates described above. The conventional semiconductor devices which are formed on the semiconductor wafer include capacitors, resistors, transistors, diodes, and the like. In advanced manufacturing of integrated circuits, hundreds of thousands of these semiconductor devices are formed on a single semiconductor wafer.
The computer and electronics industry is constantly under market demand to increase the speed at which integrated circuits operate, to increase the capabilities of integrated circuits, and to reduce the cost of integrated circuits. One manner of accomplishing this task is to increase the density with which the semiconductor devices can be formed on a given surface area of a single semiconductor wafer. In so doing, the semiconductor devices must be decreased in dimension in a process known as miniaturization. In order to meet market demands and further the miniaturization of integrated circuits, the processes by which the semiconductor devices are formed are in need of improvement.
The capacitor is a structure which is frequently formed in integrated circuit manufacturing and for which an improved method of formation is needed. The capacitor is formed with a storage node, a cell plate, and an intervening dielectric layer. The storage node and the cell plate are typically patterned out of polysilicon by conventional photolithography and dry etching. The dielectric layer is formed in an intervening process between the formation of the storage node and the cell plate, typically by chemical vapor deposition (CVD) of silicon nitrite through exposure of the polysilicon of the storage node to oxygen at an elevated temperature.
An important consideration in forming capacitors in integrated circuits is surface area. A large surface area of the storage node and cell plate is necessary in order to provide high capacitance and therefore optimal performance of the capacitor. Balanced against this need is the competing requirement that the capacitor also occupy a minimum of space on the silicon substrate of a semiconductor wafer on which the capacitor is formed. One manner in which the semiconductor industry has approached minimal space capacitor formation is to form the capacitor at a significant distance above the silicon substrate. When so doing, one of the storage node and the cell plate are typically wrapped around the other, forming what is known as a stacked capacitor.
While the use of stacked capacitors has effectively increased capacitor surface area, one further problem common with the various configurations of stacked capacitors and the processes used to form them is that the processes are generally complicated and lengthy, thereby increasing the opportunities for defect conditions to occur and driving up integrated circuit manufacturing cost. Generally, the greater the surface area provided by the process, the more elaborate and expensive the process is.
Thus, even stacked capacitors are reaching the limits of usable surface area that can be provided in a cost effective manner.
Consequently, an improved method is needed which forms a capacitor of a large surface area and which forms the capacitor in a manner that occupies a minimum of space on the silicon substrate. In addition, such a method is needed which can be conducted in a simple and cost effective manner.
A method is provided herein for forming a silicon structure on a semiconductor substrate with a pair of exposed surfaces that are roughen ed so as to increase the surface area thereon. In one embodiment a capacitor storage node is formed with roughen ed inner and outer opposing surfaces which together provide increased surface area and increased charge retention.
The method of the present invention initially involves providing a semiconductor substrate and forming thereon a charge conducting region to which the capacitor storage node will be electrically connected. In the embodiment to be discussed, the semiconductor substrate comprises a silicon substrate of a semiconductor wafer and the charge conducting region comprises an active region located on the semiconductor substrate. Also in the embodiment to be discussed, a pair of gate stacks are formed on the silicon substrate, one at either side of the active region, and a polysilicon plug is formed between the gate stacks and in electrical connection with the active region. An insulating layer is formed over the gate stacks, the polysilicon plug, and the active region. The insulating layer is plagiarized to a height that corresponds to a height to which the capacitor storage node is to extend above the gate stacks. A recess is formed in the insulating layer above the semiconductor substrate where the capacitor is to be formed.
Subsequently under the method of the present invention, a volume of silicon-containing material is formed so as to line the sides and bottom of the recess. In the embodiment being discussed, the volume of silicon-containing material comprises a polysilicon layer that is preferably formed as a blanket layer that partially fills the recess. A portion of the polysilicon layer is also formed on the surface of the insulating layer above the recess. The polysilicon layer is formed with a thickness selected in accordance with a desired thickness of a free-standing wall of the capacitor storage node that is to be formed.
Once the polysilicon layer is formed, a layer of hemispheric al grain polysilicon (HSG) or cylindrical grain polysilicon (CSG) is deposited on the surface thereof, preferably with chemical vapor deposition (CVD). The layer of HSG or CSG polysilicon provides a roughen ed texture of the surface of the layer of polysilicon.
An alternative technique for providing a roughen ed texture of the surface of the layer of polysilicon is a seed and anneal process. In the seed and anneal process, CVD of a silicon hydride such as silane is used to deposit the silicon hydride upon the surface of the polysilicon layer. A heat treatment process caused the silane to mobilize the silicon material of the silane so as to agglomerate into crystals. The result is a roughen ed texture.
Next, the portion of the polysilicon layer that was formed on the surface of the insulating layer is removed. To do so, a height reduction process is conducted, and in preparation for the height reduction process, the recess is filled with photo resist or other suitable protective material. The photo resist or other suitable material protects the portion of the polysilicon layer lining the sides and bottom of the recess from being removed or contaminated by the height reduction process. Once the recess is filled with the protective material, the height reduction process is conducted to remove the portion of the polysilicon layer that was formed on the surface of the insulating layer. Preferably, the height reduction process is a polarization process. More preferably, the height reduction process is a chemical-mechanical plagiarizing (CMP) process. The photoresist or protective material is then removed.
Ions are implanted into the polysilicon layer with an ion implantation process. The ion implantation process is conducted with an implantation energy that implants a substantially higher concentration of ions into an upper portion of the polysilicon layer than it implants into a lower portion of the polysilicon layer. The preferable angle of implantation of the ions with respect to the surface of implantation is as close to ninety degrees (90), given the limitation of the aspect ratio of a recess into which ion implantation is made. An implantation energy is selected in conjunction with the angle of ion implantation so as to implant ions into the polysilicon layer at a desired implantation depth. The desired implantation depth corresponds to a thickness of a resulting wall of a capacitor storage node that is to be formed from the polysilicon layer.
The ion implantation process is in one embodiment conducted in multiple stages. Ion implantation parameters such as the angle of implantation and the implantation energy are varied between the stages to tailor the resulting ion concentration profile of the implanted portion of the polysilicon layer.
In one embodiment, the insulating layer is removed after the ion implantation process is concluded. Thereafter, an etching process which is selective to implanted silicon-containing material is conducted to remove the lower portion of the polysilicon layer. One etching process which is selective to implanted silicon-containing material comprises immersing the semiconductor wafer in an enchant comprising tetrameter ammonium hydroxide (TMAH). The TMAH enchant is preferably prepared with a concentration of about 2.5 weight percent TMAH in a solution of deionized water.
The lower portion of the polysilicon layer is removed by the etching process and the upper portion of the polysilicon layer remains in place and forms a free-standing wall that is in electrical communication with the underlying charge conducting region. In the embodiment being discussed, the free-standing wall forms the capacitor storage node. In one embodiment wherein the recess which was formed in the insulating layer is circular, the free-standing wall has a closed cross-sectional shape, such as a circle, an ellipse, an oval, or an annular shape.
Once the capacitor storage node is formed, conventional process flow is followed to complete a capacitor. Briefly, completion of a capacitor involves forming a dielectric layer over the free-standing wall of the storage node and forming a cell plate over the dielectric layer from polysilicon or another charge conducting material.
In an alternate embodiment, the insulating layer is not removed after conducting the ion implantation process. Consequently, once the selective etching process is conducted, a capacitor storage node is formed within the recess in the insulating layer. The dielectric layer and cell plate are then formed in a region of open space between the capacitor storage node and the edges of the recess.
Thus, the method of the present invention forms a capacitor storage node that has roughened inner and outer opposing surfaces which provide increased surface area such that the capacitor storage node occupies minimal space on the silicon substrate of the semiconductor wafer. The method is simple and can maintain conventional throughput and cost levels of the integrated circuit manufacturing process.
These and other features and advantages of the present invention will more fully apparent from the following description and appended claims, or learned by the practice of the invention as set forth hereinafter.